In the semiconductor industry, feature sizes of components on an integrated circuit (IC) package have become smaller in order to minimize a footprint of the IC package, while also decreasing a power demand associated with the IC package. Such a decrease in feature size and power demand, however, places significant demands on semiconductor processing capabilities. In the recent past, it has proven difficult to keep up with the demand for such a continued decrease in minimum feature sizes while maintaining a small footprint of the final IC package.
One technique used for minimizing a footprint of an IC package is called Package on Package (POP) processing, wherein two or more individual component IC dies are arranged or stacked vertically in a single package. Vertically interconnecting multiple IC dies to act as a single IC chip or package generally shortens an interconnection distance between individual component IC dies, thereby improving processing speed and reducing power consumption.
In a conventional POP process, one or more top dies are vertically stacked over a bottom die and/or intermediate substrate in order to minimize the footprint of the final IC package. Solder bumps are sometimes provided on a bottom surface of the top die in a Ball Grid Array (BGA), wherein the solder bumps are melted or “reflowed” once the top die is stacked on the bottom die and/or an intermediate substrate, therein electrically connecting the top die to the bottom die and/or intermediate substrate. In general, alignment of the top die to a specific pattern on the bottom die and/or intermediate substrate is performed manually, with a separate placement of each respective top die onto the bottom die and/or substrate. Achieving proper alignment during reflow operations has thus far proven to be difficult.